@Assembler Programming Topics :8086 architecture Intel 8086 Family Architecture % General Purpose Registers Segment Registers AH/AL AX (EAX) Accumulator CS Code Segment BH/BL BX (EBX) Base DS Data Segment CH/CL CX (ECX) Counter SS Stack Segment DH/DL DX (EDX) Data ES Extra Segment (FS) 386 and newer (Exx) indicates 386+ 32 bit register (GS) 386 and newer % Pointer Registers Stack Registers SI (ESI) Source Index SP (ESP) Stack Pointer DI (EDI) Destination Index BP (EBP) Base Pointer IP Instruction Pointer % Status Registers FLAGS Status Flags (see FLAGS) % Special Registers (386+ only) CR0 Control Register 0 DR0 Debug Register 0 CR2 Control Register 2 DR1 Debug Register 1 CR3 Control Register 3 DR2 Debug Register 2 DR3 Debug Register 3 TR4 Test Register 4 DR6 Debug Register 6 TR5 Test Register 5 DR7 Debug Register 7 TR6 Test Register 6 TR7 Test Register 7 % Register Default Segment Valid Overrides BP SS DS, ES, CS SI or DI DS ES, SS, CS DI strings ES None SI strings DS ES, SS, CS - see CPU DETECTING Instruction Timing :Instruction Timing Instruction Clock Cycle Calculation Some instructions require additional clock cycles due to a "Next Instruction Component" identified by a m" in the instruction clock cycle listings. This is due to the prefetch queue being purge on a control transfers. Below is the general rule for calculating "m": 88/86 not applicable 286 "m" is the number of bytes in the next instruction 386 "m" is the number of components in the next instruction (the instruction coding (each byte), plus the data and the displacement are all considered components) 8088/8086 Effective Address (EA) Calculation % Description Clock Cycles Displacement 6 Base or Index (BX,BP,SI,DI) 5 DisplacementBase or Index) 9 Base+Index (BP+DI,BX+SI) 7 Base+Index (BP+SI,BX+DI) 8 Base+Index+Displacement (BP+DI,BX+SI) 11 Base+Index+Displacement (BP+SI+disp,BX+DI+disp) 12 - add 4 cycles for word operands at odd addresses - add 2 cycles for segment override - 80188/80186 timings differ from those of the 8088/8086/80286 % Task State Calculation "TS" is defined as switching from VM/486 or 80286 TSS to one of the following: New Task 486 TSS486 TSS386 TSS386 TSS286 TSS Old Task (VM=0) (VM=1) (VM=0) (VM=1) À 386 TSS (VM=0) 309 226 282 386 TSS (VM=1) 314 231 287 386 CPU/286 TSS 307 224 280 486 CPU/286 TSS 199 177 180 ÀÙ % Miscellaneous - all timings are for best case and do not take into account wait states, instruction alignment, the state of the prefetch queue, DMA refresh cycles, cache hits/misses or exception processing. - to convert clocks to nanoseconds divide one microsecond by the processor speed in MegaHertz: (1000MHzn MHz)) = X nanoseconds - see 8086 Architecture :directives:asm directives Macro Assembler Directives Processor Code Generation Directives .186 enables assembly of 80186 instructions .286 enables assembly of non privileged 80286 instructions .286C same as .286 .286P enables assembly of all 80286 instructions .287 enabled assembly of 80287 instructions Continua »